Electrical and Electronic Engineering Technologists and Technicians Salary

The median electrical and electronic engineering technologists and technicians salary in the United States is $78,190 per year ($37.59/hour). Salaries range from $49,510 at the entry level to $115,700+ for the top 10% of earners. There are 95,130 electrical and electronic engineering technologists and technicians jobs nationwide. Employment is projected to grow 0.6% through 2034.

Last updated: June 2026 Β· Source: U.S. Bureau of Labor Statistics

Median Salary
$78,190
per year
Hourly Rate
$37.59
per hour
Employment
95,130
jobs in the U.S.

Salary Distribution

10th percentile
$49,510
25th percentile
$61,610
Median
$78,190
75th percentile
$97,650
90th percentile
$115,700

Job Growth (2024-2034)

+0.6%
Slower than average

Annual Openings

8,400
jobs/year (growth + replacements)

Education Required

Associate's degree

Electrical and Electronic Engineering Technologists and Technicians Career Guide

Interview questions, resume templates, and a career ladder written specifically for electrical and electronic engineering technologists and technicianss.

Electrical and electronic engineering technologists and technicians build, test, calibrate, and repair the hardware that engineers design β€” prototype PCB boards, semiconductor test benches, RF and power lab setups, avionics units, factory-floor controls, and instrumentation. They do the board bring-up, PCB rework, waveform capture, ATE (Automated Test Equipment) programming, and failure-analysis grind that separates a design on paper from a design that ships. BLS pegs the occupation at 95,130 employed with median $78,190, p10 $47,700, p90 $118,320. Entry Technician I / Test Technician pay is $46-58k; established Technician II / III is $62-82k; Sr Technician / Lead Test Tech is $78-105k; Sr Failure Analysis Technician / Lab Manager at defense primes and semiconductor houses hits $95-135k+. Defense (Northrop Grumman, Raytheon, Lockheed Martin, L3Harris, BAE Systems) and semiconductor (TSMC, Intel, Micron, Texas Instruments, Analog Devices) pay 10-20% above BLS median. IPC-A-610 (acceptability of electronic assemblies), IPC-7711/7721 (rework and repair), J-STD-001 (soldering requirements), and NASA-STD-8739 (hi-rel soldering) certifications are the credential ladder β€” a J-STD-001 Space Addendum-certified rework tech at a defense prime tops the occupation's pay scale.

Core Skills Hiring Managers Screen For

Test bench operation β€” oscilloscope, spectrum analyzer, VNA, source measure unit, DMM
Drive a Tektronix MSO series (MSO54 / MSO58 / 5B) or Keysight InfiniiVision (MSOX3054T / DSOX6004A) past auto-trigger β€” probe compensation, impedance selection, math channels, protocol decode (I2C / SPI / UART / CAN / USB / PCIe). Spectrum analyzer (Keysight N9020B MXA, Rohde & Schwarz FSW) for RF emissions and harmonic analysis; VNA (Keysight PNA, Rohde & Schwarz ZNB) for S-parameters. SMU (Keysight B2900 / Keithley 2400) for I-V curves.
PCB rework and repair (IPC-7711/7721) β€” SMT, BGA, fine-pitch
Hot air rework station (Metcal HCT-1000, Hakko FR-810B, PACE ThermoFlo TF-1500) for BGA and QFN work; soldering iron (Metcal MX-5250, JBC CD-2SHE, Hakko FX-951) for through-hole and fine-pitch SMT; solder paste and stencil rework; conformal coating removal and reapplication (Humiseal 1B31, 1A33, 2A64). Repair a 0402 or 01005 pad lift, replace a BGA, and requalify per IPC-A-610 Class 2 or Class 3.
ATE programming and test-fixture bring-up (Teradyne, Advantest, National Instruments)
Program automated test equipment β€” Teradyne UltraFLEX for semiconductor test, Advantest V93000 for IC test, National Instruments TestStand and LabVIEW for benchtop and production test. Bring up a test fixture, debug pin-map issues, and validate first-article against gold-unit reference.
Failure analysis (FA) β€” visual, electrical, mechanical, cross-section
Systematic FA methodology per JEDEC JEP131 or vendor-specific procedures. Visual inspection (Keyence VHX-7000 digital microscope, Olympus BX53 metallurgical microscope), electrical test (curve tracer, DMM, thermal camera FLIR / Fluke), mechanical (X-ray inspection Yxlon FF35, Nordson DAGE 6300), cross-section (LeitzTM RM2265 saw + polish + microscope inspection). Root-cause a solder-joint failure, an ESD kill, a moisture-ingress issue, or a manufacturing defect.
Board bring-up (power sequencing, reset, boot log capture, JTAG / SWD)
First-article board bring-up procedure: (1) power rails at each stage of the sequencing tree, (2) reset and clock verification on scope, (3) boot-log capture over UART, (4) JTAG / SWD chain check via Segger J-Link, ST-Link, or Lauterbach TRACE32. Every new board rev goes through this. A skilled bring-up tech saves an EE 8-40 hours per rev.
Cable and harness assembly (IPC-WHMA-A-620), crimp / connector work
Crimp tooling (AMP / TE Connectivity, Molex, JST connector systems), pull-force testing per J-STD-001, harness fabrication per IPC-WHMA-A-620 Class 2 or Class 3, potting and cable-strain relief. Aerospace and defense harness work is high-margin and skill-gated.
Documentation and traveler discipline β€” test procedures, redlines, RMA reports
Every touch on a board or unit is logged in a traveler (Confluence, PLM systems like Windchill or Teamcenter, or a paper traveler at older shops). Test procedures written to a repeatable standard so any technician can re-execute. Redlines to schematics and PCB drawings signed off by the responsible EE and captured in the PLM.
ESD handling, MSL (moisture sensitivity level), and cleanroom protocol
ESD wrist strap + heel strap + mat + ionizer at every bench per ANSI/ESD S20.20. MSL parts (moisture-sensitive components like BGAs) baked before rework per J-STD-033. Cleanroom protocol (Class 1000 or Class 10,000) at semiconductor and medical-device shops β€” gowning, particle count, no cardboard, no notebook paper.

How to Become a Electrical and Electronic Engineering Technologists and Technicians

  1. 1
    Earn an Associate's degree in Electronics Engineering Technology (EET) or Electrical Engineering Technology from an ABET-accredited program
    2-year degree; ~$5-25k tuition depending on public vs private. ABET accreditation matters at defense primes and semiconductor houses. Some employers accept a 4-year BS in EET as equivalent to a 2-yr AAS + 2-3 years experience.
  2. 2
    Alternative path β€” military electronics rating + transition to industry
    US Navy Electronics Technician (ET), Fire Controlman (FC), Aviation Electronics Technician (AT); US Air Force Avionics Systems; US Army 94E / 94F Electronics Repairer; US Coast Guard ET. Military-trained ETs are highly sought at defense primes and often bypass the associate's degree requirement.
  3. 3
    Start as Technician I / Test Technician at $46-58k
    Typical early roles: test bench operator at a semiconductor or defense shop, PCB rework tech at a manufacturing site (Foxconn, Jabil, Flex, Sanmina), board bring-up assistant at an OEM engineering lab.
  4. 4
    Earn IPC-A-610 (acceptability of electronic assemblies) and J-STD-001 (soldering requirements) at Class 2 or Class 3
    IPC-A-610 and J-STD-001 are the baseline PCB workmanship certifications. Class 2 = general electronics; Class 3 = high-reliability (aerospace, medical, military). $300-600 per cert + $150-300 renewal every 2 years. Employer typically pays.
  5. 5
    Move to Technician II / III at $62-82k
    3-6 years experience. Own PCB rework end-to-end (SMT, BGA, fine-pitch), drive test-fixture bring-up, execute board-level bring-up autonomously. Cross-train on a specialty β€” RF lab, high-voltage safety, semiconductor probe stations, or thermal imaging.
  6. 6
    Earn IPC-7711/7721 (rework and repair) and IPC-CIT (Certified IPC Trainer) or the Space Addendum for defense
    IPC-7711/7721 is the rework and repair standard; IPC-CIT lets you train and certify other technicians (a strong Sr Technician resume item); J-STD-001 Space Addendum is the highest solder-quality standard, required at NASA-heritage defense primes.
  7. 7
    Advance to Sr Technician / Lead Test Tech / Failure Analysis Sr Technician at $78-105k
    8-15 years. Lead 2-6 technicians, own the certification pipeline for the team, drive continuous improvement on lab and rework processes, own the failure-analysis process end-to-end for the product line.
  8. 8
    Optional path β€” BS EET completion + transition to Test Engineer or Manufacturing Engineer at $85-125k+
    Some experienced technicians complete a BS EET (usually employer-subsidized under Section 127 up to $5,250/yr federal tax-free) and transition to Test Engineer, Manufacturing Engineer, or Applications Engineer roles at $85-125k+ base. This is a real ladder step, not a lateral move.

Career Progression

Technician I / Test Technician / Rework Technician I
0-3 yrs$46-62k base + $2-5k shift differential at 24/7 shops
  • β€’Execute test procedures on the bench under a Sr Technician or Test Engineer's supervision β€” oscilloscope, DMM, spectrum analyzer
  • β€’Board-level rework (SMT to 0603 and QFN); learn BGA and fine-pitch under mentor supervision
  • β€’Complete traveler documentation for every unit through the lab or rework line
  • β€’Complete IPC-A-610 Class 2 (or Class 3 at defense shops) and J-STD-001 Class 2 in first 90 days
Next: Technician II at 2-4 years after IPC-A-610 + J-STD-001 certifications and first autonomous rework quals.
Technician II / Test Technician II
3-6 yrs$62-82k base + $3-6k shift differential
  • β€’Autonomous board-level rework including BGA and fine-pitch SMT (0402 and 01005)
  • β€’Own test-fixture bring-up for new products; debug pin-map and functional issues
  • β€’Execute failure-analysis workflow β€” visual, electrical, and cross-section β€” with a Sr Technician's sign-off
  • β€’Cross-train on a specialty (RF, high-voltage, thermal imaging, semiconductor probe)
Next: Sr Technician / Technician III at 5-8 years with IPC-7711/7721 certification.
Sr Technician / Lead Test Technician / Lead Rework Technician
6-12 yrs$78-105k base + $5-10k shift differential + $2-8k annual bonus at public co
  • β€’Lead a bench or line of 2-6 technicians; hold the daily standup, distribute work, and own the shift metrics
  • β€’Own the failure-analysis process end-to-end for the product line; call out root-cause and corrective actions to the responsible Design or Test Engineer
  • β€’IPC-CIT (Certified IPC Trainer) or J-STD-001 Space Addendum certified; drive certification pipeline for the team
  • β€’Represent the technician team in design-review and manufacturing-review meetings
Next: Sr Failure Analysis Technician / Lab Manager at 10-16 years (IC track) or Test / Manufacturing Engineer via BS EET completion (engineer fork).
Sr Failure Analysis Technician / Lab Manager / Manufacturing Test Manager
12-20 yrs$95-135k+ base + 8-15% bonus + $10-40k RSU at public co (Micron, Intel, TI)
  • β€’Own the failure-analysis lab or the manufacturing-test line β€” 8-30 technicians, 3-8 test benches, 1-3 rework cells
  • β€’Drive lab-wide continuous improvement β€” reduce first-pass-yield loss, cut FA cycle time, improve traveler discipline
  • β€’Own capital-equipment planning for the lab (next-gen scope, X-ray inspection, VNA, cross-section equipment)
  • β€’Chair the technician career-development committee; own the mentor and IPC-CIT pipeline
Next: Engineering Manager (Test / Manufacturing Test / Failure Analysis) at 18-25 years β€” the manager fork.
Test Engineer / Manufacturing Engineer / Applications Engineer (via BS EET completion)
8+ yrs$85-125k+ base + 10-15% bonus + $15-60k RSU at public co
  • β€’Design test-fixture hardware and test procedures for new products
  • β€’Develop LabVIEW or Python test scripts running on National Instruments or in-house test frameworks
  • β€’Own DFT (design for test) and DFM (design for manufacturability) reviews for new products
  • β€’Bridge design-engineering and manufacturing / test β€” the technicians who transition to this role often become the most productive engineers because they understand the physical layer
Next: Sr Test Engineer / Sr Manufacturing Engineer at 12-18 years, then Staff Engineer or Manager at 18-25 years.

Interview Questions & Answers

5 free questions below. Career Kit unlocks 15 total plus resume bullets for every level.

Q1. Walk me through a board bring-up you did β€” from power-on to first successful boot.technical
Structure by step: (1) Pre-power-on checks β€” visual inspection for solder bridges or missing components, DMM continuity across power rails to catch short-to-ground before you smoke the board. (2) Power on at reduced current limit (bench supply at 500 mA limit) β€” measure each power rail against the sequencing tree on the schematic, verify voltage and ramp time on a Tektronix MSO. (3) Reset and clock β€” verify the reset signal and the 20 or 40 MHz reference oscillator on scope. (4) JTAG / SWD chain check via Segger J-Link β€” read the IDCODE of every device in the chain. (5) Boot-log capture over UART at 115200 baud β€” save to log file. (6) First bug I found β€” power rail rippling because a decoupling cap was 100 nF instead of the specified 1 uF; scoped V_out on Tek MSO54 with 200 MHz probe, root-caused in 15 minutes, fixed by hand-swap and requalified. (7) Signed off the traveler and handed the board back to the responsible EE. A weak answer is generic; a strong answer cites the actual instrument, the actual bug, and the actual fix time.
Q2. How do you rework a BGA?technical
Systematic. (1) Preheat the board on a preheater (Metcal HCT-PP1000 or PACE ThermoFlo TF-1500) to 100-125C to reduce thermal shock. (2) Mount the BGA site under a hot-air nozzle sized to the package (10-15 mm nozzle for a 10x10 mm BGA). (3) Apply the profile β€” reflow the solder balls (typically 217C for SnAgCu, 138C for SnBi), lift the BGA with vacuum pen. (4) Clean the pad site β€” de-solder braid the remaining solder to a smooth pad; inspect under 20x microscope for pad damage. (5) Reball or reuse the BGA β€” reball with a stencil and solder paste, or use a pre-balled replacement. (6) Apply flux to the pad site, place the BGA, reflow with the same profile. (7) X-ray inspect (Nordson DAGE 6300 or Yxlon FF35) to verify ball joint integrity and no shorts. (8) Requalify the board electrically and update the traveler. Skilled turnaround: 45-90 minutes for a standard BGA; 2-4 hours for a large package or a package-on-package. Interviewers screen for whether you cite the actual station, the profile parameters, and the X-ray inspection step.
Q3. Describe your failure-analysis approach.technical
Systematic. (1) Reproduce the failure β€” if it's intermittent, run a Shmoo plot (voltage vs temperature) on a Keithley 2400 SMU to characterize the failure envelope. (2) Visual inspection first (Keyence VHX-7000 or Olympus BX53 microscope) β€” often the answer is right there (cold solder joint, cracked cap, delaminated conformal coat). (3) Electrical characterization β€” pin-by-pin curve tracer or DMM against a known-good gold unit. (4) X-ray inspection for hidden defects β€” BGA voiding, wire-bond issues, capacitor delamination. (5) Cross-section if warranted β€” Leitz RM2265 saw + polish + microscope to see the solder joint interior or the die bond. (6) Document the root cause in the FA report with photos, waveforms, and the specific corrective action recommendation. (7) Present findings to the responsible design or process engineer. My typical FA cycle time is 3-8 days per unit at defense-prime standards. Interviewers value candidates who walk through the JEDEC JEP131 FA framework, not just Looked at it under a microscope.
Q4. Why electronics technician β€” not electrical engineer?culture
Honest answer that lands: you like hands-on work more than schematic design. You like the immediate feedback loop of the bench β€” the scope waveform tells you within minutes whether your hypothesis is right β€” and you value building physical skills (rework, cable harness, cross-section) that not everyone can do. You know the pay ceiling is lower than an EE with a BS + PE, but you also know the top-of-scale rework or FA technician at a defense prime hits $95-125k without the 4-year degree and the design-review meetings. If you're planning to transition to BS EET + Test Engineer later, say so β€” it's a legitimate ladder step and interviewers respect it. Avoid vague love electronics β€” every candidate says that. Cite a specific rework or FA case that hooked you.
Q5. Where do you see your career in 5 years?closer
Show the ladder. Sr Technician on your primary bench or line, IPC-CIT certified so you train and certify the next generation, J-STD-001 Space Addendum if you're at a defense prime. Lab Manager or Lead Test Tech at year 10-14 with team-of-6 responsibility. Or the engineering fork β€” completing a BS EET on employer tuition reimbursement (Section 127 up to $5,250/yr federal tax-free plus employer top-up), transitioning to Test Engineer or Manufacturing Engineer at $85-125k+ at year 12-15. Vague growth answers screen out; concrete ladder awareness screens in.

Resume Template β€” Sr Technician / Lead Test Technician (6-12 yrs)

Copy these bullets into your resume as a starting point. Career Kit includes bullets for every level of the ladder.

Sr Technician / Lead Test Technician (6-12 yrs)
  • β–ΈSr Test Technician on the RF bench at [defense prime β€” Northrop Grumman / Raytheon / L3Harris]; owned board bring-up, VNA characterization, and failure analysis for 3 avionics product families qualified to DO-160.
  • β–ΈCut FA cycle time from 8.2 days to 4.6 days average by standardizing the JEDEC JEP131 workflow and rebuilding the cross-section prep procedure; documented playbook adopted lab-wide.
  • β–ΈIPC-A-610 Class 3 + J-STD-001 Class 3 + J-STD-001 Space Addendum + IPC-7711/7721 + IPC-CIT + NASA-STD-8739. AAS Electronics Engineering Technology, [ABET-accredited program].
  • β–Έ$92k base + $5k shift differential + $3k performance bonus + active DoD Secret clearance at [employer]; mentored 4 Technician Is through IPC-A-610 and J-STD-001 Class 3 certification.

What Gets You Rejected

  • βœ—Bench discipline gaps β€” can't drive an oscilloscope past auto-trigger, doesn't know 1x vs 10x probe compensation, or has never used a network analyzer or spectrum analyzer.
  • βœ—ESD sloppiness β€” no wrist strap at the bench, cardboard on the workspace, or handling MSL parts without bake tracking. Hard pass at semiconductor and defense shops.
  • βœ—No IPC certifications despite 3+ years at a PCB-heavy employer β€” either coasting or the employer doesn't invest, and both are red flags on the resume.
  • βœ—Sloppy traveler / documentation β€” can't articulate the traveler workflow, doesn't sign off on unit test results, doesn't understand the paper trail matters at defense and medical shops.
  • βœ—Cannot cross-train β€” Technician II who won't move beyond their primary specialty (test bench, rework, FA) caps at $75-85k for their career.
  • βœ—No safety fluency β€” can't articulate HV lock-out-tag-out, laser safety at semiconductor probe stations, or arc-flash risk at industrial-control benches.

Salary Negotiation Levers

  • βœ“IPC certification stack β€” J-STD-001 Class 3 lifts pay 5-10% over Class 2; adding Space Addendum lifts another 5-10% at defense shops. IPC-CIT (Certified IPC Trainer) lifts pay 5-8% and is required for lead technician roles.
  • βœ“NASA-STD-8739 (hi-rel soldering) β€” 8-15% premium at NASA-heritage defense primes (Northrop Grumman Space, Lockheed Martin Space, JPL contractors, Raytheon Space & Airborne Systems).
  • βœ“Cleared work premium β€” active DoD Secret clearance adds $8-20k base at defense primes; Top Secret / SCI adds $20-45k. Never let a clearance lapse.
  • βœ“Metro premium β€” Silicon Valley (Intel, Nvidia, AMD, Broadcom), Austin (Samsung, Applied Materials, ARM, Texas Instruments), Phoenix (TSMC Arizona, Intel, ON Semiconductor, Microchip), San Diego (Qualcomm), Boston (Analog Devices, Raytheon, MIT Lincoln Lab), Los Angeles (Northrop Grumman, Raytheon, JPL), and Seattle (Boeing, Microsoft Hardware) pay 15-30% above BLS national median.
  • βœ“Specialty premium β€” RF, high-voltage, semiconductor probe, and thermal-imaging specialists earn 10-15% above general-purpose bench technicians. Cross-training on 2 specialties lifts 10-15%.
  • βœ“Shift differential β€” nights typically 10-15% at 24/7 semiconductor and defense shops; weekends 15-25%. Non-negotiable at most union shops; negotiable at non-union.
  • βœ“BS EET tuition reimbursement β€” Section 127 up to $5,250/yr federal tax-free plus employer top-up at most Fortune 500. Ask for the full policy in writing at hire.
  • βœ“Sign-on bonus β€” $2-15k common at Sr Technician level in tight labor markets; larger ($10-30k) if you carry an active clearance or J-STD-001 Space Addendum that the employer needs.

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Electrical and Electronic Engineering Technologists and Technicians Salary by State

Best Cities (cost-adjusted) β†’

Salary Map β€” Click a state for details

$58K
$100Kβ–  No data
StateMedianvs. National
Wyoming$99,840+27.7%
Rhode Island$98,600+26.1%
District of Columbia$97,620+24.8%
Hawaii$96,200+23.0%
New Mexico$96,070+22.9%
Maryland$95,830+22.6%
Washington$93,930+20.1%
Alaska$92,760+18.6%
Nevada$88,160+12.8%
California$86,090+10.1%
1–10 of 51

Electrical and Electronic Engineering Technologists and Technicians Salary by Metro Area

Metro AreaMedianvs. National
Bremerton-Silverdale-Port Orchard, WA$106,250+35.9%
Atlantic City-Hammonton, NJ$103,480+32.3%
Bakersfield-Delano, CA$103,170+31.9%
Lexington Park, MD$102,640+31.3%
Baton Rouge, LA$102,380+30.9%
Albuquerque, NM$102,250+30.8%
Casper, WY$99,840+27.7%
Seattle-Tacoma-Bellevue, WA$98,180+25.6%
Lake Charles, LA$97,740+25.0%
Oxnard-Thousand Oaks-Ventura, CA$97,680+24.9%
1–10 of 243
Data Source: U.S. Bureau of Labor Statistics, Occupational Employment and Wage Statistics (OEWS). Data reflects the most recent annual survey.
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View Electrical and Electronic Engineering Technologists and Technicians salary trend (2011–2024) β†’